ON THE REDUCTION OF THE THIRD ORDER DISTORTION IN A CMOS TRIODE TRANSCONDUCTOR - Circuits and Systems, 1996., ISCAS '96, 'Connecting the World'., 1996 IEEE International Symposium

This paper presents a linearisation technique which aims to cancel out the third order distortion of a CMOS triode transconductor due to the mobility reduction effect of the conversion transistors. The transconductor consist of a parallel operating voltage and current biased differential pair. It is realised in a 0.8pm CMOS process. Simulation results, obtained with state-of-the-art MOS models, show a significant deviation from the measurement results. It is shown that the third order distortion prediction of the generally used ‘8-model’ for mobility reduction is rather poor in the triode region. W with: KO = p.C,, .L Saturation region (vds 2 Vgs V,): If Vds is constant in the triode region, Id is linear with Vgs [ 11. In the saturation region the sum or the difference of Vgs of two transistors must be constant for a linear V to I conversion [2,3]. According to this model the synthesised circuits have a perfectly linear transfer function. However due to second order effects the linearity of such circuits is limited. In a balanced circuit the even order distortion will cancel out, however odd order distortion will not cancel out. Especially the mobility reduction effect introduces significant third order distortion. The mobility reduction effect can be modelled by the ‘8-model’ which is obtained by replacing I?, by &ff in eq. 1, where: